library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div5M is 
port(clkin:in std_logic;
     clkout:buffer std_logic);
end;

architecture rtl of  div5M is
begin
	process(clkin)
	variable count:integer range 0 to 24999999;
	begin
		if clkin'event and clkin='1' then
			if count=24999999 then
				clkout<=not clkout;
				count:=0;
			else count:=count+1;
			end if;
		end if;
	end process;
end;
